The present invention relates to an analog-to-digital converter circuit capable to being included in a semiconductor integrate circuit. More specifically, the present invention relates to a successive approximation mation analog-to-digital converter circuit capable being operated at a high speed with high accuracy.
The successive approximation analog-to-digital converter circuit conventionally used has a digital-to-analog conversion circuit, which is formed of a resistor string in which a plurality of resistors are connected in series, as a reference voltage generation circuit. Hereinafter, the resistor string will be referred to as "resistor circuit" and the digital-to-analog conversion to "D/A conversion".
In this case, if a parasitic resistance is present at electrode portions of both ends of the resistor circuit, the parasitic resistance has an effect upon the voltage between intermediate terminals of the resistor circuit, in other words, a reference voltage generated at both ends of a unit resistor constituting the resistor circuit, with the result that the resultant voltage is smaller than normally obtained. Therefore, the D/A conversion code converted from an analogous input voltage by using the D/A conversion circuit includes an error corresponding to a voltage drop due to the parasitic resistance.
To avoid the decrease in conversion accuracy due to the parasitic resistance, it may be considered that the resistance of the resistor circuit constituting the D/A conversion circuit is increased. However, the high resistance is a big drawback to attaining the high speed conversion. Alternatively, it may be considered that resistances of unit resistors corresponding to the most significant and least significant sides of the resistor circuit are lowered in consideration of the parasitic resistance. However, since the resistances vary depending upon variation of process conditions, it is extremely difficult to set the resistances accurately.
Now, referring to FIG. 1, problems of the conventionally-used D/A conversion circuit will be explained in detail.
The DAC block shown in the leftmost column of FIG. 1 indicates a resistor circuit constituted of a plurality of unit resistors connected in series. The DAC block is a main constitutional element of the D/A conversion circuit generating a reference voltage for determining the D/A conversion code.
However, in practice, parasitic resistances R.sub.L, R.sub.H are present respectively between the DAC block and each of two end terminals of the DAC block, one for applying a reference voltage (generating a reference voltage) V.sub.REFL at a low voltage side and the other for applying a reference voltage V.sub.REFH at a high voltage side.
FIG. 1 (at the upper right portion) schematically shows the relationship between the potential distribution V.sub.dac of the D/A conversion circuit (mainly composed of the DAC block having parasitic resistances at both ends) and the A/D conversion code determined by using the potential distribution. Note that "00H" and "FFH" plotted on the longitudinal axis are the A/D conversion code in terms of hexadecimal notation. A broken line indicates the case where the parasitic resistances R.sub.L, R.sub.H are absent. The solid line corresponds to the case where the parasitic resistances are present.
As shown in the graph, when the parasitic resistances are absent, a simple proportional relationship is established between the potential distribution V.sub.dac and the A/D conversion code. Whereas, when the parasitic resistances are present, a voltage drop due to the presence of the parasitic resistances R.sub.L, R.sub.H has an effect upon both ends of the potential distribution. Since the A/D conversion code is determined based upon the potential distribution, an error is included. Since the graph is drawn assuming that R.sub.L is equal to R.sub.H, an error is not presented in the middle of the graph. However, since R.sub.L is not equal to R.sub.H in practice, the solid line shown in the graph is evenly (equally) deviated from the broken line (hereinafter, referred to "off-set error").
If a product obtained by multiplying a theoretical value of the A/D conversion code obtained on the basis of the case without the parasitic resistance by a voltage of the least significant bit, is represented by V.sub.DAC, an analogous input voltage input into the analog-to-digital circuit is represented by V.sub.AIN, and an overall conversion error is represented by V.sub.err =V.sub.dac -V.sub.AIN, V.sub.dac &gt;V.sub.DAC at the low voltage side, and V.sub.dac &lt;V.sub.DAC at the high voltage side are obtained as shown in FIG. 1, at a lower right side. To obtain a correct code, V.sub.dac must be reduced at the low voltage side of the DAC block and V.sub.dac must be increased at the high voltage side.
Referring now to FIG. 2, operation of the successive approximation A/D converter circuit conventionally used will be schematically explained. The successive approximation A/D converter circuit shown in FIG. 2 is constituted of a voltage comparing circuit 1, a D/A conversion circuit 4, and an A/D conversion control circuit 5.
To the successive approximation A/D converter circuit, an analogous input voltage V.sub.AIN is input. The D/A conversion circuit 4 outputs the voltage V.sub.dac D/A-converted from the DAC block. The voltage comparing circuit 1 compares the analogous input voltage V.sub.AIN with the D/A converted voltage V.sub.dac . The A/D conversion control circuit 5 has a register circuit for determining and holding a predetermined data corresponding to one-bit of the D/A conversion code depending upon the output from the voltage comparing circuit 1.
The A/D conversion control circuit 5 repeats the comparing/determining operation per bit from the most significant bit (MSB) to the least significant bit (LSB) of the D/A conversion code. The D/A conversion code finally determined, in other words, a DAC code 5a shown in FIG. 2, is output to the D/A conversion circuit 4. In this manner, the D/A conversion code is held in a register circuit as an A/D conversion data.
To explain more specifically, the successive approximation A/D converter circuit comprises a sample-hold condenser C.sub.SH connected to one of input terminals of the voltage comparing circuit 1, a reference condenser C.sub.ref connected to the other input terminal of the voltage comparing circuit 1, a switch SW.sub.SH connected to one of the terminals of the sample-hold condenser C.sub.SH, for switching the analogous input voltage V.sub.AIN and the D/A converted voltage V.sub.dac from each other, and switches SW.sub.AZN, SW.sub.0, SW.sub.AZP directly connected to the sample-hold condenser C.sub.SH and the reference condenser C.sub.ref by bypassing the voltage comparing circuit 1. The switches SW.sub.AZN, SW.sub.0, SW.sub.AZP are simultaneously turned on during a sample-hold period.
An arrow of the broken line 3 indicates that a plurality of switches are operated in connection with each other between the sample-hold period and the period (hereinafter, referred to as "comparing period") in which V.sub.AIN and V.sub.dac are compared with each other in the voltage comparing circuit 1, as in the aforementioned manner.
In the sample-hold period, the switch SW.sub.SH is connected to a V.sub.AIN side. Simultaneously, the switches SW.sub.AZN, SW.sub.0, SW.sub.AZP are turned on and C.sub.SH, and C.sub.ref are connected in series. As a result, the C.sub.SH, and C.sub.ref are rapidly charged with a potential difference between V.sub.AIN and V.sub.REFH.
When the sample-hold operation by the sample-hold condenser C.sub.SH is completed, the switches SW.sub.AZN, SW.sub.0, SW.sub.AZP are turned off, whereby the bypass of the voltage comparing circuit 1 is opened and the voltage comparing circuit 1 becomes active. As a result, voltage V.sub.opn and V.sub.opp (V.sub.opn) obtained before the opening are maintained at the differential input.
More specifically, the sample-hold voltage of the analogous input voltage V.sub.AIN is transferred to + input voltage V.sub.opp of the voltage comparing circuit 1 by the switching operation, and maintained by C.sub.ref over the comparing periods sequentially performed from MSB to LSB.
During the comparing period, the switch SW.sub.SH is connected to the V.sub.dac side. In a first comparing operation, V.sub.dac corresponding to the most significant D/A conversion code is output to the D/A conversion circuit 4. V.sub.dac is compared with the analogous input voltage V.sub.AIN for magnitude by the voltage comparing circuit 1. If V.sub.dac &gt;V.sub.AIN, the MSB of the corresponding D/A conversion code is determined as "0". IF V.sub.dac &lt;V.sub.AIN, the MSB of the D/A conversion code is determined as "1". The comparison is repeated in the same manner until LSB of the A/D conversion code of V.sub.AIN is determined. As a result, the conversion codes of the overall bits providing V.sub.AIN are determined.
Next, we will explain the successive comparing process from a first MSB until n-th LSB is determined, by taking an n-bit (n is an integer of 1 or more) successive approximation A/D converter circuit conventionally used, as an example. In addition, we will explain why an error is generated between V.sub.DAC (a theoretical value of the A/D conversion code) and V.sub.dac (obtained in practice) if parasitic resistances R.sub.H, R.sub.L are included in the D/A conversion circuit.
In the first-time comparing operation, if a voltage of a (-) input terminal of the voltage comparing circuit 1 is V.sub.opn, a voltage of a (+) input terminal of the voltage comparing circuit 1 is V.sub.opp (=V.sub.opn), and the electric charge to be supplied to a condenser C.sub.SH is Q.sub.total, then a charge equation is given by EQU Q.sub.total =C.sub.SH (V.sub.opn -V.sub.AIN) (1).
Furthermore, if the output from the D/A conversion circuit 4 in i-th (i is an integer of 1 or more) process of the successive comparing process is V.sub.dac (i), an input voltage to a (-) side of the voltage comparing circuit 1 is V.sub.opn '(i), and electric charge of C.sub.SH is Q.sub.total ', then, a charge equation is given by EQU Q.sub.total '=C.sub.SH {V.sub.opn '(i)-V.sub.dac (i)} (2).
In the circuit shown in FIG. 2, if V.sub.AIN &gt;V.sub.dac (i), V.sub.opn (=V.sub.opp)&gt;V.sub.opn '(i). Therefore, the i-th D/A conversion code determined in the i-th time comparison becomes "1".
On the other hand, if V.sub.AIN &lt;V.sub.dac (i), V.sub.opn (=V.sub.opp)&lt;V.sub.opn '(i). Therefore, the i-th D/A conversion code determined in the i-th time comparison becomes "0".
Since the D/A conversion code is converted to satisfy V.sub.opn (=V.sub.opp)=V.sub.opn '(i) in accordance with the aforementioned procedure in the successive conversion, V.sub.dac (i) output from the D/A conversion circuit 4 is approximated to V.sub.AIN. The charge held by the sample-hold condenser C.sub.SH can be maintain during all periods including the sampling period and comparing period (Q.sub.total =Q.sub.total '). The D/A conversion voltage V.sub.dac (n) at the time the A/D conversion of the analogous input voltage V.sub.AIN is completed, is given by the following equations (1) and (2): EQU C.sub.SH {V.sub.opn -V.sub.opn '(n)-V.sub.AIN +V.sub.dac (n)}=0 (3).
In this case, if V.sub.opn =V.sub.opn '(n), then, the following equation is given: EQU V.sub.dac (n)=V.sub.AIN (=V.sub.DAC -.DELTA.V) (4).
In other words, if the D/A conversion code is obtained by using the conventional D/A conversion circuit 4 including the parasitic resistances R.sub.L, R.sub.H, the output V.sub.dac (n) of the D/A conversion circuit 4 approximates to the analogous input voltage V.sub.AIN. However, in the case, the error (.DELTA.V) explained by use of the rightward figure of FIG. 1 remains between V.sub.dac (n) and the theoretical value V.sub.DAC. Therefore, it is impossible that the analogous input voltage V.sub.AIN is consistent with the D/A conversion voltage V.sub.DAC corresponding to the A/D conversion code theoretically obtained.
The conventional successive converter circuit has the resistor circuit in which a plurality of resistor circuits connected in series, as a constitutional element of the D/A conversion circuit. However, when the resistor circuit has parasitic resistance at both ends, an error is inevitably produced in the A/D converter circuit to be output.